阻塞赋值

（d = a+b）在前，（out = d+c）在后

module block_nonblock(Clk, Rst_n, a,b,c, out);

	input Clk;
	input Rst_n;
	input a,b,c;
	
	//out = a + b + c;
	output reg [1:0]out;
	
	//d = a + b
	//out = d + c;
	reg [1:0]d;
	
	always@(posedge Clk or negedge Rst_n)
	if(!Rst_n)
		out = 2'b0;
	else begin
		d = a + b;
		out = d + c;
	end

endmodule

（out = d+c）在前，（d = a+b）在后

module block_nonblock(Clk, Rst_n, a,b,c, out);

	input Clk;
	input Rst_n;
	input a,b,c;
	
	//out = a + b + c;
	output reg [1:0]out;
	
	//d = a + b
	//out = d + c;
	reg [1:0]d;
	
	always@(posedge Clk or negedge Rst_n)
	if(!Rst_n)
		out = 2'b0;
	else begin
		out = d + c;
		d = a + b;
	end

endmodule

非阻塞赋值

（d <= a+b）在前，（out <= d+c）在后

module block_nonblock(Clk, Rst_n, a,b,c, out);

	input Clk;
	input Rst_n;
	input a,b,c;
	
	//out = a + b + c;
	output reg [1:0]out;
	
	//d = a + b
	//out = d + c;
	reg [1:0]d;
	
	always@(posedge Clk or negedge Rst_n)
	if(!Rst_n)
		out <= 2'b0;
	else begin
		d <= a + b;
		out <= d + c;
	end

endmodule 

`timescale 1ns/1ns
`define tp 1 //模拟电路延时
module block_nonblock(Clk, Rst_n, a,b,c, out);

	input Clk;
	input Rst_n;
	input a,b,c;
	
	//out = a + b + c;
	output reg [1:0]out;
	
	//d = a + b
	//out = d + c;
	reg [1:0]d;
	
	always@(posedge Clk or negedge Rst_n)
	if(!Rst_n)
		out <= #`tp 2'b0;
	else begin
		d <= #`tp a + b;
		out <= #`tp d + c;
	end

endmodule

（out <= d+c）在前，（d <= a+b）在后

module block_nonblock(Clk, Rst_n, a,b,c, out);

	input Clk;
	input Rst_n;
	input a,b,c;
	
	//out = a + b + c;
	output reg [1:0]out;
	
	//d = a + b
	//out = d + c;
	reg [1:0]d;
	
	always@(posedge Clk or negedge Rst_n)
	if(!Rst_n)
		out <= 2'b0;
	else begin
		out <= d + c;
		d <= a + b;
	end

endmodule

阻塞赋值与非阻塞赋值区别

阻塞和非阻塞赋值的区别在：阻塞是顺序执行，而非阻塞是并行执行。